In a dynamic random access memory (“DRAM”), data is stored as a logic high value (e.g., “1”) or logic low value (e.g., “0”) by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as a charge on the capacitor, the charge gradually leaks off and the data becomes corrupted. Therefore, a “refresh” cycle must be performed before sufficient time passes for the data to become corrupt, to maintain the integrity of the data. The frequency at which the memory cell needs to be refreshed depends upon several factors including the quality of the signal, i.e., the amount of charge on the capacitor that is able to be stored in memory. For example, if a logic “1” value is being stored, the quality of signal is dependent upon the amount of charge placed on the capacitor during the write operation. The greater the amount of charge on the capacitor, the higher the quality of the “1” signal. In contrast, if a “0” is being stored in memory, the signal is of higher quality if there is no charge on the capacitor. A higher quality of the signal enables the memory cell to be refreshed less frequently which ultimately leads to less power consumption and less data corruption.
To refresh data from a memory array, the array is typically placed in a read mode to obtain the data currently stored in a row of memory cells. Subsequently, these data are used as new input data that are re-written into the row of memory cells, thus maintaining the stored data.
FIG. 1 illustrates a prior art DRAM circuit 100 having a first bit cell 108 and a second bit cell 102. The value stored in the first bit cell 108 is passed to the bit line BL through PMOS transistor 106. The value stored in the second bit cell 102 is passed to the bit line bar ZBL through PMOS transistor 104. The first and second PMOS transistors 106, 104 are coupled to sense amplifier 120. Sense amplifier 120 includes a pre-charge circuit 122, a back-to-back inverter 130 and two NMOS transistors 108, 110, which have their gates tied to column selection line SL. Pre-charge circuit 122 is comprised of three NMOS transistors 124, 126, 128, each of which has its gate tied to equalization line EQ.
Back-to-back inverter 130 is a conventional cross-coupled CMOS inverter comprising two PMOS transistors 132, 134 and two NMOS transistors 136, 138, NMOS transistors 136 and 138 have low threshold voltages for reasons discussed below. The gates of NMOS transistor 138 and PMOS transistor 134 are tied together and coupled to both the bit line bar ZBL and the drains of NMOS transistor 136 and PMOS transistor 132, which are also tied together. The gates of NMOS transistor 136 and PMOS transistor 132 are tied together and coupled to the bit line BL and the drains of NMOS transistor 138 and PMOS transistor 134, which are also tied together. The sources of PMOS transistors 132 and 134 are tied together and connected to high voltage source VDD via line SP and PMOS transistor 140, which has its gate tied to control line CL1. The sources of the NMOS transistors 136 and 138 are also tied together and connected to VSS, which is set at ground, via line SN.
The refreshing of a “1” in the first bit 108 of prior art DRAM circuit 100 is now discussed. Initially, circuit 100 is in the “normal operation” mode, where the circuit 100 is not refreshing, reading or writing. In this mode, equalization line EQ is coupled to a logic “1” signal, which turns on the three NMOS transistors 124, 126, 128 of pre-charge circuit 122 and pre-charges ZBL and BL to the voltage of VBL. VBL is approximately half the voltage (relative to VSS) of VDD. Also in this mode, back-to-back inverter 130 is off as CL1 has a high voltage signal connected to it, turning off PMOS transistor 140. Next, the refresh mode begins by transitioning the voltage on equalization line EQ from a high voltage to a low voltage, causing lines ZBL and BL to float at approximately VBL. Additionally, PMOS transistor 106 is turned on by transitioning word line WL from a high voltage to a low voltage. The voltage of the first bit 108 is then coupled to BL. Since BL has a bit line capacitance that is larger than the capacitance of capacitor 108, the voltage of BL is pulled up slightly.
Next, back-to-back inverter 130 is turned on by transitioning the voltage on control line CL1 from a high voltage to a low voltage, thereby turning on PMOS transistor 140 and coupling line SP to VDD. When sense amplifier 130 is turned on, the voltage on bit line BL is pulled up via PMOS transistor 134, and the voltage of bit line bar ZBL is pulled down via NMOS transistor 136.
FIG. 2 is a diagram showing voltage versus time and illustrates certain signals of DRAM circuit 100 as they transition during the normal operating phase and the refresh phase. Of particular interest are the signals of lines BL and ZBL as they illustrate the slow transitioning from their initial voltage level at VBL at time t=1 to their respective voltage levels at VDD and VSS at time t=2. As illustrated in FIG. 2, the transition of both BL and ZBL from their initial voltage to their final voltages is slow, as the slopes of the lines indicate a gradual transition,
Because it is difficult to completely pull the voltage of the capacitor 108 to its maximum voltage by turning on the back-to-back inverter by lines SN and SP, the frequency for refreshing the PMOS transistor 106 must be increased so the data stored in the capacitor 108 is retained, Similar problems exist with regards to refreshing a “0” value in bit cell 108. The sequence of refreshing a “0” in bit 108 is similar to the process described above with regards to refreshing a logic “1” in bit cell 108. When a logic “0” is being refreshed, it is difficult to remove all of the charge from capacitor 108. Therefore, the frequency of refreshing the bit must be increased.
To help increase the ability of VSS to pull down the voltage on line BL during the refreshing phase of a “0” in storage bit 108, NMOS transistors 136, 138 are typically low threshold voltage transistors. Manufacturing circuits with different threshold voltages requires additional manufacturing processing, as all of the transistors of the circuit cannot be formed by the same steps. The additional manufacturing steps, such as additional photolithographic steps, drive up the time and cost of production.
Therefore, it is desirable in the art to provide an improved apparatus and method.